This invention relates to a comparator circuit for converting a voltage difference appearing between a first and a second input terminal of the comparator circuit during a first state of a clock signal into a voltage difference appearing between a first and a second output terminal during a second state of the clock signal. The comparator circuit comprises an input differential amplifier having a non-inverting input and an inverting input and having an inverting output and a non-inverting output, which outputs are coupled respectively to the first and the second output terminal of the comparator circuit. First switching means apply the voltage difference appearing between the first and the second input terminal during the first state of the clock signal to the non-inverting input and the inverting input respectively. A first and a second capacitor are coupled respectively between the inverting output and a first node and between the non-inverting output and a second node.
Such a comparator circuit can be used inter alia in an analog to digital converter.
A comparator circuit of this type is known from U.S. Pat. No. 4,553,052. In a first state of the clock signal a differential amplifier and a comparator determine whether an input signal is larger or smaller than a certain reference signal. In a second state of the clock signal a decision is made whether an output signal of the differential amplifier is to be transferred to a latch circuit. A resolution realised by an analog to digital converter depends, inter alia, on the accuracy with which the comparators used in the converter can discriminate between the input signal and the reference signal. The accuracy is limited, inter alia by an offset voltage appearing between the inputs of the differential amplifier. One possibility of improving the accuracy of the comparators is to reduce the offset voltage of the differential amplifier. In the known comparator circuit an offset reduction is achieved in that in the first state of the clock signal a voltage difference amplified by the differential amplifier and appearing between the input terminals of the comparator circuit plus the equally amplified offset voltage is stored in capacitors arranged between a reference voltage and the outputs of the differential amplifier. Subsequently, in the second state of the clock signal the inputs of the differential amplifier are interconnected, so that only the offset voltage of the differential amplifier is amplified, the capacitors being connected between the outputs of the differential amplifier and the output terminals of the comparator circuit respectively. Addition of the charge of the capacitors results in a voltage difference across the output terminals which is independent of the offset voltage of the differential amplifier. This voltage difference controls the latch circuit, which latch circuit consequently indicates at its output terminal which of the two outputs of the differential amplifier carries the higher voltage. In these circuits it is essential that the voltage difference to be detected and appearing on the capacitors is maintained in order to preserve the information about this voltage difference during the transition from the first state of the clock signal to the second state of the clock signal. In the known comparator circuit the capacitors are charged in the first state of the clock signal and are isolated from their charging path in the second state of the clock signal. This isolation from the charging path is effected by means of MOS transistors, which usually results in differences of the injected channel charge owing to the spread in area and threshold voltage of the MOS transistors. These differences constitute the limiting factor in the design of comparator circuits.